1 Field of the Invention
The invention herein relates in general to a trace layout of a printed circuit board (PCB) and more particularly to a PCB provided with an accelerate graphics port (AGP) slot and a peripheral component interconnect (PCI) slot, wherein the AGP and PCI traces can be effectively laid out.
2. Description of the Related Art
Referring to FIG. 1, which shows a conventional trace layout of a PCB with the AGP and PCI traces, including a central processing unit (CPU) slot 100, a north bridge 110, an AGP slot 120, four PCI slots 130, and a south bridge 140. The north bridge 110 and the south bridge 140 are both intelligent control chipsets. The north bridge 110 is mainly connected to devices which process data at high data rate and high efficiency while the south bridge 140 is connected to peripheral devices functioning at low data rate. In the conventional trace layout, the AGP slot 120 is located between the PCI slots 130 and the north bridge 110. The north bridge 110 is directly connected to the AGP slot 120 by the AGP traces 150 (150A and 150B). As shown in FIG. 1, the PCI traces 160 (160A and 160B) connecting the north bridge 110 to the south bridge 140 is designed to trace aside the AGP slot 120, pass through the PCI slots 130, and finally connect to the south bridge 140.
Conventionally, the PCB has a multi-layer structure composed of a component layer, a ground layer, a power layer, and a solder layer. As mentioned above and depicted in FIG. 1, the AGP traces 150 further includes traces 150A (real lines) which are distributed on the component layer and traces 150B (dotted lines) which are distributed on the solder layer. Similarly, the PCI traces 160 are composed of traces 160A (real lines) which are distributed on the component layer and traces 160B (dotted lines) which are distributed on the solder layer. However, the above-mentioned trace layout of PCB, spatial utilization has been optimized such that miniaturization of the PCB size is impossible.
It is therefore an object of the invention to provide a trace layout of a PCB, wherein the trace layout flexibility is increased significantly. By modifying the trace layout for the AGP and PCI traces, the gap between the AGP slot and the CPU slot can be reduced. As a result, the size and the cost of the PCB can be reduced while the efficiency of the whole PCB is still preserved.
In order to accomplish the object of the invention, the invention provides a trace layout of a PCB. The PCB, including at least a first trace layer and a second trace layer under the first trace layer, is provided with a north bridge, at least a PCI slot, and an AGP slot. The AGP slot is mounted between the north bridge and the PCI slot. The PCB further includes a number of first traces for connecting the north bridge to the PCI slot, and a number of second traces for connecting the north bridge to the AGP slot. Some of the first traces are distributed on the second trace layer under the AGP slot and trace aside the AGP high-frequency signal differential pairs. The differential pairs include the first address/data strobe differential pair (AD_STB0 and - AD_STB0), the second address/data strobe differential pair (AD_STB1 and - AD_STB1), and the side-band strobe differential pair (SB_STB and - SB_STB). The other of the first traces are on the first trace layer or the second trace layer and trace aside the AGP slot. Most of the second traces are on the first trace layer, and only the other of the second traces are on the second trace layer. In the above mentioned trace layout, the gap of the traces between the CPU and AGP slots can either be reduced or the reserved space can be further used for placement of other devices. The cost effectiveness of the whole PCB is then improved.
In order to accomplish the object of the invention, the invention further provides a trace layout of a PCB. The PCB, including at least a first trace layer and a second trace layer under the first trace layer, is provided with a control chipset, at least a bus slot, and a fast processing chip slot. The fast processing chip slot is located between the control chipset and the bus slot. The PCB further includes a number of first traces and a number of second traces. The first traces are used to connect the control chipset to the bus slot. Some of the first traces are on the second trace layer and under the fast processing chip slot, while the other of the first traces are on the first trace layer or the second trace layer and trace aside the fast processing chip slot. The second traces are used to connect the control chipset to the fast processing chip slot. Most of the second traces are on the first trace layer, and the other of the second traces are on the second trace layer. The cost effectiveness of the PCB is then improved.